This invention relates to a novel PLL (Phase-Locked Loop) synthesized scanning radio receiver controlled by a CPU (Central Processing Unit) via a keyboard. More particularly, the present invention relates to a scanning radio receiver which is intended to simplify the structure thereof, without sacrificing the high performance of the scanning radio receiver.
In order to control various functions of the radio receiver, a CPU is usually included with the receiver. Additionally, a keyboard is usually included with the receiver to enable an operator to give various commands or instructions to the CPU in order to operate the radio receiver. It is then possible for the operator to set a reception objective frequency, via the keyboard, into the radio receiver in order to attain the desired or targeted reception objective frequency.
FIG. 1 illustrates an example of a conventional radio receiver having a CPU 10 and a keyboard 12, in which a radio wave of a designated frequency can be tuned, by keying in that designated frequency into the keyboard, in order to reproduce its modulating audio signal. This radio receiver is constructed as a double superheterodyne system having means for converting the received radio wave signal into a first IF (Intermediate Frequency) signal and then further converting the first IF signal to a second IF signal, the second IF signal having a lower frequency than that of the first IF signal.
More specifically, a radio wave signal is received by an antenna 14, the frequency of which is keyed in from the keyboard 12, and is adapted to pass through either a VHF RF amplifier 16 or a UHF RF amplifier 18, depending upon the radio wave signal's frequency. If the frequency of the radio wave signal or reception objective signal, which is keyed in from the keyboard, is within the VHF frequency range, the VHF RF amplifier 16 is activated and the UHF RF amplifier 18 is deactivated, whereby the reception objective signal can pass through the activated VHF RF amplifier 16. Conversely, if the frequency of the reception objective signal, which is keyed in from the keyboard, is within the UHF frequency range, the VHF RF amplifier 16 is deactivated and the UHF RF amplifier 18 is activated, whereby the reception objective signal can pass through the activated UHF RF amplifier 18. The decision as to which RF amplifier 16 or 18 is activated or deactivated, may be made by the provision of an activating or deactivation signal on lines 17 and 19, respectively, from the CPU 10 depending upon the frequency of the reception objective wave signal which is keyed in from the keyboard.
The VHF reception objective signal which has passed through the activated VHF RF amplifier 16 is then applied to a first VHF mixer 20 so that the VHF reception objective signal is frequency-converted to be provided as a first IF signal of 10.7 MHz. Similarly, the reception objective signal which has passed through the activated UHF RF amplifier 18 is applied to a first UHF mixer 22 so that the UHF reception objective signal is frequency-converted to be provided as the first IF signal of 10.7 MHz. This first IF signal is then amplified by a first IF amplifier 24 which is tuned to the 10.7 MHz frequency range, and applied to a second mixer 26 in which the first IF signal is frequency-converted to a second IF signal of 455 KHz by the use of a 10.245 MHz beat frequency signal generated from a local oscillator 28. The second IF signal of 455 KHz is then passed through a band-pass filter (not shown) for increasing selectivity, amplified by a second IF amplifier (not shown), and detected in order to reproduce an audio signal.
In such a superheterodyne system, a great number of frequencies are required to be applied to the first mixer 20 or 22 in order to convert the frequency of the VHF or UHF reception objective wave signal into the 10.7 MHz first IF signal frequency. For example, if the receiver can receive the VHF low band ranging over 30 to 54 MHz in 5 KHz increments, 4,800 beat frequencies are needed, and if the receiver can receive the VHF high band ranging over 136.005 to 174 MHz in 5 KHz increments, 7,599 beat frequencies are needed. For the reception of the UHF band of 380 to 512 MHz in 12.5 KHz increments, 10,560 beat frequencies must be applied to the first mixer 22 for the UHF band.
In the conventional radio receiver, as illustrated in FIG. 1, these beat frequencies are generated by a PLL frequency synthesizer circuit which includes a first VCO (Voltage Controlled Oscillator) 30 for generating lower frequencies and a second VCO 32 for generating higher frequencies. The outputs of these VCO's 30 and 32 are applied through a buffer amplifier 34 to the VHF mixer 20, and only the output of the VCO 32 is applied the UHF mixer 22 through a frequency tripler 36 of which activation is controlled by the CPU 10. Control signals for selectively operating the VCO's 30 and 32 are applied from the CPU 10 through lines 31 and 33, respectively. The PLL frequency synthesizer circuit further includes a reference divider circuit 38 to which a stable frequency source 40 such as a temperature compensated crystal, is connected, a comparison divider circuit 42, a phase comparator 44 which receives the outputs of the reference and comparison divider circuits 38 and 42, a low-pass filter 46 of which output is connected to the control input of the VCO's 30 and 32, and a prescaler 48 connected between the output of the buffer amplifier 34 and an input of the comparison divider circuit 42. The reference and comparison divider circuits, 38 and 42, receive a series of clock, data, and latch signals through lines 50, 52, and 54, respectively, from the CPU 10.
The reference divider circuit 38 comprises, for example, a 14-bit shift register, a 14-bit latch and a 14-bit binary counter. The comparison divider circuit 42 comprises, for example, a 17-bit shift register consisting of a 7-bit shift register and a 10-bit shift register, a 17-bit latch consisting of a 7-bit latch and a 10-bit latch, and a 7-bit swallow and 10-bit programmable counter combination. In operation, each rising edge of the clock signal from the CPU 10 shifts one bit of the data signal from the CPU 10 into the 14-bit and 17-bit shift registers. The last data bit (control bit) entered determines which latch of the 14-bit and 17-bit latches is activated; one logic (for example, "H") selects the 14-bit reference latch and the other logic (for example, "L") selects the 17-bit comparison latch. One logic (for example, "H") of the latch signal from the CPU 10 latches the data from the shift register into the reference or comparison latch depending on the control bit of the data. For example, if the control bit is at a logic high, the reference latch is activated, and if the control bit is at a logic low, the comparison latch is activated. The contents transferred to the respective latches provide dividing ratios of the respective divider circuit. The output of the prescaler 48 acts as a clock input for the 7-bit swallow and 10-bit programmable counter combination, and for example, a rising edge signal decrements the swallow and programmable counters. A stable frequency from the stable frequency source 40 is applied to the 14-bit reference counter as its clock. The output frequency (fr) of the reference counter, constituting the output of the reference divider circuit 38, and the output frequency (fc) of the comparison counters, constituting the output of the comparison divider circuit 42, are phase-compared in the phase comparator 44. For example, if frequency (fc), is greater than (fr), or if the phase of (fc) is leading, then the phase comparator 44 provides negative pulses as error information; if the frequency (fc), is less than (fr), or if the phase of (fc) lagging, then the phase comparator 44 provides positive pulses as error information; and if the frequency of (fc)=(fr), and both are in phase, then the phase comparator 44 provides a high impedance output.
If a dual-modulus prescaler is used for the prescaler 48, a control logic circuit is used in connection with the comparison counters to control the dual-modulus prescaler, and generates a signal therefor. For example, the level of this signal is low at the beginning of a count cycle and remains low until the 7-bit swallow (.div.A) counter has counted down from its programmed value. At this time, the dual-modulus prescaler control signal goes high and remains high until the 10-bit programmable (.div.N) counter has counted the rest of the way down from its programmed value (N-A=Total dual-modulus prescaler control signal high time, since the (.div.N) counter simultaneously counts down during the (.div.A) counter count down period during the first portion of the cycle). The dual-modulus prescaler signal is then set back low, the counters reset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value of (NT)=N*P+A where P and P+I represent the dual-modulus prescaler divide values respectively for high and low modulus control levels, N being the number programmed into the (.div.N) counter, and A being the number programmed into the (.div.A) counter. For example, MC145158-2 manufactured and sold by Motorola as a serial-input PLL frequency synthesizer IC includes such reference divider circuit 38, comparison divider circuit 42 and phase comparator 44.
With this conventional circuit structure, it is possible for the radio receiver to receive a limited range of radio wave signals in the VHF low band (30-54 MHz) or the VHF high band (138-174 MHz) and the UHF band (380-512 MHz). However, there is a demand for a wider frequency range radio receiver which can cover wide frequency ranges such as 30-54 MHz (or 68-88 MHz), 118-174 MHz, 380-512 MHz, and 806-960 MHz, for example, with a relatively simpler construction. The present invention presents such a radio receiver. Other features and advantages of the present invention will become apparent upon a reading of the attached specification.